Advanced Wafer Thinning Technology and Feasibility Test for 3D Integration

Introduction The semiconductor industry is now facing a major turning point in how to realize the next generation of large-scale integration. Recently 3D integration (3DI) using through-silicon via (TSV) has widely studied and wafer thinning has been considered to be a promising technology for enhancing system performance instead of conventional two-dimensional (2D) scaling due to technical and economical issues. 3DI technology also provides benefits to reduce interconnect delay, form factor, and power consumption (Fig. 1). Moreover recent attention has focused on productivity and the costs involved in volume production. Wafer scale 3DI technology, so-called Wafer-on-a-Wafer (WOW), characterized by thinning-first before bonding TSV-last process and Cu multilevel TSV interconnects, has been developed [1, 2]. Stacking at the wafer level significantly increases the processing throughput, and low aspect ratio and " bumpless " TSVs give excellent contact yield as well as lower via stress (Fig. 2). There need further optimization of total thickness variation (TTV) in the stacking module. This paper describes high resolution grinding process for ultra-thinning using DGP8761 (DISCO) with in-situ thickness measurement (Auto-TTV, NCG = non-contact gauge). Wafer thinning effect for logic devices on mobility, gettering, and switching charge characteristics are discussed. Results and Discussion Figure 3 shows schematic diagram of grinding process. Wafer thickness uniformity after grinding is determined by contact angle between wheel and wafer surface. Since wafer is very slightly bowed and bonded on temporary adhesives, those uniformities reflect to the contact angle. In case of ununiform contact angle, thinned wafer thickness is varied resulting in large TTV (Fig. 3-a). With optimizing contact angle using Auto-TTV and NCG methods, lower TTV is achieved because wafer surface was adjusted geometrically to wheel head (Fig. 3-b). As a result, contact angle decides TTV reaching to 0.5 um of 300 mm wafer as shown in Figure 4. With the ultra-thinning process, 300 mm wafer having 45-nm node high-performance logic device was evaluated, in which device has strained transistors and Cu/low-k multilevel interconnects. Silicon wafer was adhered onto support glass and thinned down to 7-um by conventional grinding and UPG. Since the hole mobility is more sensitive than that of electron for the channel strain [3], the external mechanical stress induces decreasing mobility in PMOS transistor. In this experimental, devices wafer was prepared by bonding, thinning and debonding process. It was found that the hole mobility of ultra thinned wafer down to 7-um was nearly same as that of before …